- Talk Title : Breaking the $/token barrier in LLM service : attention offloading with PIM – GPU heterogeneous system

- Abstract :
    While demand for LLM-based AI services is rising rapidly, inference cost—especially dollar-per-token—remains a key barrier. A major bottleneck is attention processing, which requires storing and computing large token caches alongside model weights within constrained GPU memory. This causes resource contention and limits batch scalability. We propose a heterogeneous architecture that offloads attention operations and token storage to a PIM-based accelerator, while GPUs focus solely on model weight execution. This separation reduces memory pressure, improves parallelism, and enables larger batches. The result is higher throughput and a dramatic reduction in dollar-per-token cost. This breakthrough makes LLM-based AI services more scalable and economically viable, accelerating real-world deployment across industries.

- Bio :
    Eui-cheol Lim is a Research Fellow and leader of Solution Advanced Technology team in SK Hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr.Lim joined SK Hynix in 2016 as a system architect in memory system R&D. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC. His recent interesting points are memory and storage system architecture with new media memory and new memory solution such as CXL memory and Processing in Memory. In particular, he is proposing a new computing architecture based on PIM, which is more efficient and flexible than existing AI accelerators, to process generative AI and LLM (large language Model).

- Talk Title : From Domain-Specific Architectures to Domain-Specific Systems in the Chiplet Era: Packaging-Aware Co-Design Across Compute and Interconnect

- Abstract :
    Domain-specific architectures have traditionally been defined by specialized compute units, optimized memory hierarchies, and tailored programming models. However, in the chiplet era, this notion is expanding as packaging technologies play a central role. The way chiplets are integrated through interposers, bonding, and vertical interconnects directly determines the bandwidth, latency, and energy efficiency of the interconnect fabric that binds domain-specific systems together. For emerging workloads such as AI, HPC, and autonomous systems, architectural design without packaging awareness risks unrealistic projections and suboptimal implementations. This talk demonstrates that domain-specific system design must expand beyond processors and accelerators to explicitly include packaging as a co-equal design parameter. We introduce a methodology that integrates physical interconnect characteristics into cycle-level architectural simulations, enabling quantitative exploration of trade-offs across chiplet partitioning, interconnect hierarchy, and workload mapping. Using chipletization as a case study, we demonstrate how packaging-aware modeling reveals fundamental insights into performance scaling, latency, and energy efficiency, and how these findings inform the construction of an open chiplet ecosystem. By elevating packaging to a first-class design parameter in domain-specific architecture research, we outline a path toward truly holistic domain-specific systems for the next generation of computing.

- Bio :
    Jiho Kim is a third-year Ph.D. student in Electrical and Computer Engineering at the Georgia Institute of Technology, advised by Prof. Cong (Callie) Hao in the Sharc Lab. Her research focuses on high-level synthesis (HLS), 2.5D/3D chiplet-based systems, and architecture–packaging co-design. In particular, she develops technology-aware simulation frameworks to enable accurate design-space exploration for emerging heterogeneous chiplet systems. She was a research intern at IBM Research in 2024 and a visiting scholar at ETH Zürich in the summer of 2025. She is a recipient of the Qualcomm Innovation Fellowship 2025 and the SK Hynix Global Fellowship. Her recent work on FPGA profiling tool was nominated for Best Paper at FCCM 2025.