- Talk Title : Reducing software friction for heterogenous systems with Revere-AMU.

- Abstract :
  One of the mitigations to the slowing of Moore's law is integrating accelerators into the system. The challenge with this approach is that it's a complex task to create a HW/SW interface that is low friction to software, even for a very simple accelerator.
  This talk will take a software view, and look at the device driver models used in heterogeneous systems. In particular we'll look at the benefits and challenges of the direct assignment model, where software interacts directly with an accelerator rather than via an operating system driver.
  While existing standards (notably, the PCI software model) can help, we believe there is a need for new industry standards to enable standard software frameworks and an ecosystem of accelerator IP components. To this end, we will describe 'Revere-AMU', an advanced development effort within Arm to identify the layers of standardisation required.

  See also blog and white paper available here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/high-performance-device-virtualization-approach-to-standardization

- Bio :
  Rob Dimond is System Architect and Fellow at Arm. Rob works in the Architecture and Technology group at Arm where his focus is developing technology in a 3-5 year time horizon for the infrastructure segment (servers and networking). Prior to Arm, Rob was Chief Hardware Architect at FPGA computing startup Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College, London.

- Talk Title : Near data processing for AI & Big data – Data hierarchy

- Abstract :
  Recently, various new services based on AI and Big data technologies are leading the evolution of computer systems, especially in deep learning based AI technologies which mimics human brain. As a result, it seems Google’s AlphaGo has beaten the human brain by winning Lee Sedol in the Go game, but in energy consumption perspective, it is still far behind the human brain. To achieve high energy efficient computation, a Neuromorphic computing concept has been introduced in the late 1980s, but it is not matured yet to deploy in real systems to provide the services.
  Since it is widely known that the more energy is required in the data movement than the data processing itself, there is a need to improve the energy efficiency in current von Neumann computing system. The Near Data Processing (NDP) concept, which places the processing power where data lives rather than moving data to processing elements, could be an one of the best candidates for the energy efficient computation. As the ecosystems (environments and conditions) changes, I believe, it will be deployed to the real system in near future. Most breakthrough momentum will be the killer application such as AI services.
  In this talk, recent trends for NDP technology will be discussed, and Data Hierarchy concept will be introduced. By adopting near data processing to every memory hierarchy, every data layer will have both memory and processing element. To bring-up data hierarchy to real world, its challenges and various research topics will be discussed as well.

- Bio :
  Eui-cheol Lim is a Research Fellow and leader of system architecture team in memory system R&D, SK Hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr.Lim joined SK Hynix in 2016 as a system architect in memory system R&D. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC. His recent interesting points are memory and storage system architecture with new media memory and memory system architecture for machine learning.

- Talk Title : Self-Aware Swarm Computiong Architectures: Domain-Specific Applications

- Abstract :
  In this presentation, I will first present the system architectural concept behind cloud-backed swarm AI: a new paradigm to support emerging new application domains (e.g. connected, intelligent autonomous vehicles, distributed power or resource management, network cyber-security, etc). I will then describe the methodology and architectural vision of a particular domain-specific software-hardware co-design project (called EPOCHS) that we are pursuing with support from the DARPA DSSoC (Domain Specific System on Chip) program. The key innovative elements of the architecture, design methodology and the enabling software stack are: (a) a systematic way to derive the hardware accelerator components of the heterogeneous SoC from the source application suite; (b) an agile FPGA integration and emulation methodology to enable early software porting; (c) a smart compiler and task-level runtime scheduler to meet real-time performance objectives at affordable power consumption; (d) a distributed chip-level power control system that leverages the swarm-AI concept applied at the system level. In describing the overall project, I will delve into aspects of the philosophical foundation supporting the goal of building self-aware (super AI) systems – those that can mimic positive human attributes of resilience and cooperative (altruistic) behavior, while avoiding common human weaknesses (e.g. lack of mental focus, illogical and unethical biases, etc.).

- Bio :
  Pradip Bose is a Distinguished Research Staff Member at IBM T. J. Watson Research Center, Yorktown Heights, NY. He has over 36 years of experience at IBM. He manages the department of “Efficient and Resilient Systems”, which has a charter of pursuing R&D in the area of technology-aware high performance computer architectures and associated modeling methodologies. His research group has a special exploratory focus on building efficient and resilient AI-centric systems in recent years. He has been involved in the pre-silicon definition and modeling of IBM POWER/PowerPC systems from the very beginning of that product family. He works with the mainframe processor development groups as well. He holds a Ph.D from the University of Illinois at Urbana-Champaign and is an IEEE Fellow. Within IBM, he holds the title of Master Inventor and he is a member of IBM’s elite Academy of Technology.

- Talk Title : Real-Time Neural Network Inference at the Edge

- Abstract :
  In recent years, dramatic improvements in mobile processing power and rapid progress in computationally efficient AI models enabled novel experiences of augmented reality effects on mobile phones. This placed on-device augmented reality technologies on a fast-paced trajectory for wide adoption.
  This talk will outline challenges and milestones in delivering live augmented reality effects to mobile devices, and present trade-offs of modern libraries for accelerated neural network inference at the edge: NNPACK library for floating-point neural network convolutions, QNNPACK library for fixed-point inference, and TensorFlow Lite GPU backend for neural network computations on mobile GPUs.

- Bio :
  Marat Dukhan is a Software Engineer in Google Research, where he works on improving efficiency of neural network inference on mobile devices. During his Ph.D. studies at Georgia Tech, Marat developed NNPACK library, which is integrated into Facebook and Snapchat AR platforms. Previously, he led development of QNNPACK library for fixed-point inference at Facebook.

- Talk Title : AI Engine in the Xilinx Adaptive Compute Acceleration Platform (ACAP)

- Abstract :
  AI inference demands orders of magnitude more compute capacity than what today’s SoCs offer. At the same time, neural network topologies are changing too quickly to be addressed by ASICs that take years to go from architecture to production. Recently Xilinx introduced Adaptive Compute Acceleration Platform with Versal as the first device family. A critical part of this architecture is AI Engine, a Domain Specific Architecture for AI inference. AI Engine offers ASIC-like performance while providing flexible memory hierarchy and custom data flow. AI Engines coupled with programmable FPGA fabric provide significant boost in AI performance, along with the hardware architecture flexibility needed to quickly adapt to rapidly evolving neural network topologies and to address whole application acceleration.

- Bio :
  Vinod Kathail is a Xilinx Fellow and the Chief Architect for the SDx Development Environment. He is also leading the company-wide focus on embedded vision including machine learning usage in edge and endpoint applications. He initiated the software programmability effort for the Zynq family, and developed and drove the adoption of SDSoC earlier on. Prior to joining Xilinx, Vinod was the founding CEO and later CTO of Synfora, a high-level synthesis startup. Vinod brings over 25 years of experience in heterogenous programming environments, high-performance parallel and VLIW architectures, parallelizing compilers and high-level synthesis, working in both research labs (HP Labs) and startups.
  Vinod received a B. Tech in Electrical Engineering from MANIT, Bhopal, a M. Tech in Computer Science from IIT, Kanpur and an ScD in Electrical Engineering and Computer Science from MIT. He holds over 25 patents, and he has authored numerous research publications.