- Talk Title : Challenges with On-Device ML at Scale

- Abstract :
   Thanks to many good reasons, we are seeing more and more machine learning workload moving to mobile and embedded devices. In this presentation, we will share various challenges in deploying the state-of-the-art machine learning research outcomes into mobile and embedded products at scale, in our computing ecosystem and discuss what we need to do as a community to address these challenges.

- Bio :
   Dong Hyuk Woo is a software engineer at Google. He is one of co-founders of the Edge TPU program at Google and currently leading Edge TPU compilation efforts. Previously, he worked as an architect for Google's cloud TPU (the first training-capable TPU), an architect in Intel's exascale computing team, and a research scientist at Intel Labs. He received his BS from Seoul National University, and his MS and Ph.D. from Georgia Institute of Technology.

- Talk Title : The eTIE Language Extension - Agile for Domain-Specific Accelerator Design

- Abstract :
   With the emergence of various application areas such as graphics, bioinformatics, deep learning, and many others, the design of domain-specific accelerators is becoming pronounced to achieve magnitude improvements in performance, cost, and power efficiency compared to the generalpurpose processors. The traditional design process for such high-performance hardware may require long design and verification cycles, and cannot keep pace with the growing requirements and fast design iterations of the hardware accelerators nowadays. Therefore, we present a novel external Tensilica Instruction Extension (eTIE) language for the domain-specific accelerators to improve the design flexibility and reduce the time-to-market. The easy-to-use eTIE language is similar to Verilog and will generate both the RTL hardware and supporting software libraries used by the compiler and simulator. With eTIE, users can enhance their design by further optimizing the Cadence Xtensa processors using new instructions and additional hardware accelerators for a particular domain of applications. In this workshop, we present the use of the eTIE language to design a rotation-based coordinate rotation digital computer (CODIC) in parallel with the Cadence Xtensa DSP core and evaluate the benefits brought by this novel design methodology.

- Bio :
   Dr. He XIAO graduated from Georgia Institute of Technology and his Ph.D. research focused on characterizing and simulating the physical effects on multi-core microarchitectures using 3DIC technology, as well as exploring adaptive architectures based on the Multiphysics analysis. His research interests include computer architecture, low power design, programming models and compiler optimization.
   Dr. XIAO currently works in IPG group at Cadence Design Systems, Inc., where he is responsible for designing and enhancing the compiler toolset for Tensilica Instruction Extension (TIE), a proprietary language that allows the users to extend the Tensilica DSP processor with custom instructions and coprocessors, to support high-performance DSP design and to explore novel architectures for application-specific acceleration.

- Talk Title : On-Device AI for Mobile and Consumer Devices: From DNN Model Compressions to Domain-Specific Accelerators

- Abstract :
  Though key AI algorithms were originally developed in decades ago, it was big data availability and hardware acceleration that really made AI so successful today. Its great successes in computer vision and speech recognition encouraged many researchers to apply AI to almost every area of science and engineering. Further, thanks to advances in model compression technologies and hardware accelerators, we are even enabling AI on low-end electronics such as washing machines.
  With on-device AI, we aim to deliver transparent AI experience on user devices without connecting to cloud servers. To enable AI functionalities on mobile and consumer devices, a system-level holistic optimization from algorithm to chip is necessary to overcome AI application’s compute, memory and power demands. We have to develop small but accurate DNN models, hardware accelerators to run the models, and runtime and compiler to manage the accelerators efficiently.
  I would like to introduce our efforts at Samsung for on-device AI systems. First, I will overview the on-device AI platform we are developing for our devices. We try to address three key technology components --- model compression, AI system SW, and AI HW accelerator. Then, I will discuss the details of our researches for each item. For model compression, we developed a fractional quantization method called FleXOR to achieve sub 1-bit compression ratio. We also developed a binary-coding based quantization method and the corresponding matrix multiplication library called BiQGEMM. For AI system SW, we are building nnStreamer that applies the stream processing paradigm to neural network processing. And, we started a light-weight training framework called nnTrainer to make on-device learning feasible for embedded devices. For AI HW accelerator, I would like discuss one of our domain-specific accelerator designs. We designed a streaming line processing architecture that enables 4K 60fps super resolution video processing (11.5 TOPS at 1 GHz). Finally, I will conclude the talk by discussing future works.

- Bio :
   Daehyun Kim is a vice president at Samsung Electronics, leading the On-Device Lab of Samsung Research. Before joining Samsung, he has been at Google and Intel working on microprocessor architecture and workload optimization for 15 years since he received the Ph.D. from Cornell University.
   His research interests include on-device AI, machine learning accelerators, mobile SoC architecture, high performance computing, intelligent memory systems, and workload analysis. Based on workload-driven architecture design, he has done path-finding research for Samsung’s on-device AI platform, Google’s Android & ChromeOS products, and Intel’s Xeon Phi coprocessors.