- Talk Title : A Structured Approach to the Hardware/Software Co-Design of an AI-Accelerator

- Abstract :
   Over the past few years, efforts to address the challenges of the end of Moore's Law has led to significant rise in AI-focused accelerators. However, the well-understood pipeline stages used in the past for designing and optimizing general-purpose processors does not apply to these accelerators. As a result, there has not been a systematic way to express the range of design features used by these accelerators. This makes it difficult to understand the impact of each design choice and compare or extend the state-of-the-art.
   In this talk, I will present a novel separation of concerns taxonomy to better understand and design AI-accelerators. One aspect of this approach is the use tensor algebraic notation to describe and optimize the computation. Second, in an analogous fashion to our prior work that categorized DNN dataflows into patterns like weight stationary and output stationary, this talk will try to provide a set of options that characterize the other attributes of tensor accelerators. Thus, rather than just presenting a single specific design, I will present a generalized framework for describing computations, dataflows and the placement of activity. In this framework, this separation of concerns is intended to better understand design choices and facilitate the exploration of the wide design space of tensor accelerators. Thus, using this common language, I will show how the choices invoked were used to generate our high-performance transformer accelerator.

- Bio :
    Joel S. Emer is a professor of Electrical Engineering and Computer Science at MIT. He also is a Senior Distinguished Research Scientistworks at Nvidia. Prior to joining Nvidia, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Previously he worked at Compaq and Digital Equipment Corporation (DEC). His current research focus is on the systematic design and modeling of accelerators. In the past, he has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of deep learning accelerator design, spatial and parallel architectures, processor reliability analysis, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and simultaneous multithreading. He earned a doctorate in electrical engineering from the University of Illinois in 1979. He received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. Among his honors, he is a Fellow of both the ACM and IEEE, and a member of the NAE. He also received both the Eckert-Mauchly award and the B. Ramakrishan Rau award for lifetime contributions in computer architecture.

- Talk Title : Programming Furiosa RNGD

- Abstract :
   AI agents are becoming kernel authors. RNGD programming must expose tensor intent and resource use to the compiler, then return correctness and execution cost to the author. RNGD Virtual ISA (vISA) expresses tensor semantics, mapping, data movement, and engine use. The furiosa-opt toolchain checks and lowers that program, then surfaces diagnostics, schedules, correctness results, and runtime profiles.
   Two RNGD case studies show programmability in practice. The NPU Model Optimization Competition gives external developers a path to build and evaluate kernels. In an internal Mistral-Nemo-12B study, an AI agent iteratively optimized kernels and the serving engine using compiler and runtime feedback, bringing performance close to the modeled attainable ceiling.

- Bio :
    Dr. Jeehoon Kang is the Chief Research Officer (CRO) at FuriosaAI. Before joining the industry, he was an Associate Professor of Computer Science at KAIST after receiving his Ph.D. under the supervision of Prof. Chung-Kil Hur at Seoul National University. As a specialist in concurrency, compilers, and software verification, he has published over 30 papers in premier venues such as MICRO, ASPLOS, SOSP, and PLDI.
   At FuriosaAI, Dr. Kang applies his academic expertise in computer systems to solve engineering challenges in industrial-scale deployment. He leads the development of kernel programming models to maximize the performance of the RNGD accelerator, alongside building the application software stack for reinforcement learning and agentic AI.

Invited Talk III

- Speaker : Daichi Fujiki (Associate Professor, Institute of Science Tokyo)