CALL FOR PAPERS
One of the most important principles in designing today's computing systems is to exploit programmability and parallelism. Mobile platforms are no exception and we find increasingly more instances of the use of programmability and parallelism in them. At the hardware level, there are: multiple processor cores, GPGPU, accelerators, multiple banks of memory, multiple channels to non-volatile memory chips, and multiple radios, to name a few. At the software level, parallel and concurrent threading techniques are commonly employed to improve responsiveness and throughput in the OS and applications alike. We anticipate that future mobile platforms will make more extensive and creative use of parallelism and programmability.
This workshop focuses on how programmability and parallelism is, and can be, utilized in hardware, software and their interaction in order to improve the user experiences with mobile platforms. Topics of particular interest include, but are not limited to:
- Emerging parallel application processor architectures and hardware features in mobile/IoT platforms;
- Mobile GPGPU architectures and programming models;
- Hardware accelerators for mobile/IoT applications;
- Storage architectures in mobile/IoT platforms;
- Radio and networking architectures in mobile/IoT platforms;
- Compiler/OS support for parallel/programmable mobile/IoT platforms;
- Experiences in mobile/IoT applications development;
- Novel techniques to improve performance/energy/responsiveness by exploiting programmability and parallelism;
- Mobile/IoT platform performance evaluation methodologies;
- Application benchmarks for mobile/IoT platforms;
- Characterization of emerging workloads on mobile/IoT platforms;
- IoT enabling technologies (smart sensors, energy harvesting, sensor networks, etc.);
- Machine learning techniques/applications and cloud systems for mobile/IoT platforms.
The workshop aims at providing a forum for researchers, engineers and students from academia and industry to discuss their latest research in designing mobile/IoT platforms and systems, to bring their ideas and research problems to the attention of others, and to obtain valuable and instant feedback from fellow researchers.
1:30 - 1:40 :Welcome and Workshop Introduction |
1:40 - 2:30 :Invited talk I: Sun Guangyu, Peking University
Design Exploration of FPGA-based Accelerators for Deep Neural Networks
2:30 - 3:00 :Sek Chai, Aswin Raghavan, SRI International, "Multi-Precision Deep Neural Networks"
3:00 - 3:30 :Break
3:30 - 4:30 :Invited talk II: Brandon Lucia, Carnegie Mellon University,
"Programming and System Support for Reliable Intermittent Computing"
4:00 - 4:30 :Vidushi Goyal, Xiaowei Wang, Valeria Bertacco & Reetuparna Das, U of Michigan
"Efficient System-In-Package Architecture for Heterogeneous Systems"(slides)
Invited talk I
- Title : Design Exploration of FPGA-based Accelerators for Deep Neural Networks (slides)
- Abstract :
Deep Neural Networks (DNNs) have been widely employed for different areas like face recognition, image classification, etc. Recently, various accelerators for DNNs have been proposed on the FPGA platform because it has advantages of high performance, reconfigurability, fast development round, etc. In this talk, I will introduce our recent research work on how to efficiently implement DNNs on FPGA based platforms. First, we propose an analytical design scheme to help us quantitatively explore the design space of DNN accelerators on single/multiple FPGA boards. Then, we design a hardware/software co-designed flow, which can be integrated with deep learning frameworks (e.g. Caffe and Tensorflow) to facilitate the DNN accelerator design on FPGAs.
Invited talk II
- Title : Programming and System Support for Reliable Intermittent Computing
- Abstract :
Emerging energy-harvesting devices (EHDs) are computer systems that operate using energy extracted from their environment, even from low-power sources like ambient radio-frequency energy. Future EHDs will be a key enabler of emerging implantable medical devices, IoT applications, and nano-satellites, but today's EHDs operate intermittently, only as environmental energy is available. Unfortunately, intermittence makes today's EHDs unreliable and extremely difficult to program and debug. In this talk I will summarize the main challenges of intermittent execution. I will then discuss our recent efforts developing system, programming language, and toolchain support for EHDs to address the challenges of intermittence, focusing especially on programmability, debugging, and reliability. I will close by discussing our recent work on building a reliable, EHD-based, hardware/software application platform for an upcoming deployment.
- Bio :
Brandon Lucia is an assistant professor in the department of electrical and computer engineering at Carnegie Mellon University in Pittsburgh, PA. Brandon's research focuses on redefining computer architectures and systems that make increasingly pervasive, often safety-critical, devices reliable, energy-efficient, and programmable. Brandon and his lab are currently focusing on defining the system stack for systems with intermittently available energy and resources, as well as on redefining parallel architectures to improve their efficiency, correctness, and reliability, exploiting heterogeneity and approximation. Brandon's work targets the boundaries between computer architecture, compilers, system software, and programming languages. Brandon's research group is supported by the National Science Foundation, Google, Intel, and Disney Research. Brandon has received a Google Faculty Research Award, the Bell Labs Prize, three IEEE MICRO Top Picks in Computer Architecture Selections, an OOPSLA Distinguished Paper Award, an OOPSLA Distinguished Artifact Award, WWW 2017 Outstanding Reviewer Award, a January 2017 People of the ACM highlight, and Brandon was elected in 2016 to serve on DARPA's Information Science And Technology (ISAT) study group. Before joining CMU, Brandon spent a year as a Researcher at Microsoft Research, Redmond. Brandon earned a Ph.D. in Computer Science and Engineering from the University of Washington in 2013, and a B.S. degree in Computer Science from Tufts University. Brandon's personal website is http://brandonlucia.com, his research group is at http://abstract.ece.cmu.edu, and his band netcat is at http://netcat.co
Submit a 2-page presentation abstract to a web-based submission system (https://cmt3.research.microsoft.com/PRISM2017) by May 8, 2017. Notification of acceptance will be sent out by May 29, 2017. Final presentation material (to be posted on the workshop web site) due June 12, 2017. For additional information regarding paper submissions, please contact the organizers.
Please refer the following format.
Abstract submission :
April 24, 2017  May 8, 2017
Author notification : May 29, 2017
Final camera-ready paper : June 12, 2017
Workshop : June 25, 2017
Sangyeun Cho, Samsung Electronics Co. (firstname.lastname@example.org)
Hyesoon Kim, Georgia Tech (email@example.com)
Hsien-Hsin Lee, TSMC (firstname.lastname@example.org)
Giho Park, Sejong Univ. (email@example.com)
Vijay Janapa Reddi, UT Austin (firstname.lastname@example.org)
Seungjin Lee, Sejong Univ. (email@example.com)
Junwhan choi, Sejong Univ. (firstname.lastname@example.org)